In all MiSTer cores, sys_top is the top level design file. You have to look at the module/entity names, not at the file names to see how they are connected. If you have looked at the code headers, you will see that each of these files was written by a different author for a different project, so you can expect that some detective work is in order to understand what is going on.Ĭonsidering the animosity between differernt HDLs, it is amazing that it is relatively easy to connect code written in different HDLs to eachother (as long as VHDL and System Verilog stoop downto the abstraction level of Verilog).
does that mean the SDRAM_A of sys_top is connected to the SDRAM_A of C64.sv? What about the size of the SDRAM. I checked other projects, this appears to be shared (as I understand it should). And this shares a little bit with what I posted as a reply in the other forum, but it's not long.
here's what I'm trying to track down right now. the SID chip design looks pulled from somewhere different. Looks like the 65C02 code is related to a 65C816 someone did. VHDL - it's going to be a matter of where the code came from - and at this point, so many of the cores or a mashup of a few different projects. According to google, this is verilog++, kinda - and includes some means to verify or test - but why is only one file. Right now, the biggest gap that I know I have is how files connect.